Sökresultat - "built-in self-test (BIST)"

Prebond TSV Detection for Coexistence of Open and Leakage Faults Based on Current Charging and Discharging

Wang, L., Dong, G., Zhi, C., Zhu, Z.

An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory

Lee, H., Lee, J., Kang, S.

An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses

Choi, W.J., Lee, M., Choi, J., Cho, J., Kim, G., Kim, B.

A Configurable Multimode Nonuniform Eye-Opening Monitor for High-Speed Wireline Communication Achieving 3-μs EW/EH Evaluation and 0.98-R² Accuracy

Han, C., Zhao, X., Wang, M., Su, X., Dong, Z., Liang, H., Liu, S., Zhu, Z.

An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis

Xiao, Z., Du, L., Yang, Z., Liu, C., Yu, Y.

An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection

Park, J., Lee, S., Kim, H., Joung, J., Kim, J., Kang, S.

Test and Diagnosis Strategies for Interchiplet Interconnects

Liu, X., Yang, D., Zhang, L., Ji, S., Yan, D., Wang, Z., Guo, Y., Wen, X., Cai, Z.

A synergistic fault tolerance framework for Mbit 28nm embedded RRAM

Papavramidou, P., Ricavy, S., Mounet, C., Jahan, C., Castellani, N., Andrieu, F.

2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)

Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment

Lin, K., Lin, O., Huang, S., Sheng, D.

High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications

Choi, J., Na, S., Kim, H., Roh, H., Cho, Y., Choi, M., Choo, M., Roh, J.

A 4-26 Gbaud Configurable Multi-Mode Non-Uniform EOM with Improved Twin PI for High-Speed Wireline Communication Achieving 3-μs EW/EH Evaluation and 0.99-R2 Accuracy

Liu, Shubin, Dong, Zhicheng, Wang, Menghao, Zhao, Xiaoteng, Han, Chenxi, Su, Xianting, Zhu, Zhangming

2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

An Efficient Grouping Algorithm with Build-in-Self-Test for Multiple Memories

Liu, Zhixing, Xu, Jielin, Tang, Jing, Yang, Song, You, Hailong

2024 2nd International Symposium of Electronics Design Automation (ISEDA)

Built in self test (BIST) for RSFQ circuits

Li, Mingye, Lin, Yunkun, Gupta, Sandeep

2024 IEEE 42nd VLSI Test Symposium (VTS)

On-Chip Characterization of Random Telegraph Signal Noise in Bulk 90 nm CMOS

Kim, J., Loveless, T. D., Pew, J., Young, R., Rcising, D., Nour, M., Manos, P., Chambers, M., Barnaby, H. J., Neucndank, J.

2024 IEEE International Reliability Physics Symposium (IRPS)

Differential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends

Wenger, Y., Ng, H.J., Korndorfer, F., Meinerzhagen, B., Issakov, V.

No-Calibration Relative Impedance and Mismatch Measurement Using Periodic Six Ports

Avci, M.E., Ozev, S., Kumar, C.

X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology

Harith, Ashrith S, Liu, Yingdi, Mukherjee, Nilanjan, Mayer, Jeff

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information

Mustafa, Y., Kose, S.

On-Chip Emulation and Measurement of Variable-Length Photocurrents in Sub-50nm ICs

D'Amico, J.V., Vibbert, S.T., Cadena, R.M., Alles, M.L., Ball, D.R., Sternberg, A.L., Zhang, E.X., Holman, W.T., Kauppila, J.S., Massengill, L.W.

Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors

Kabir, S. M Kifayat, Motalib, Raihan, Javed, Fakrul Islam, Ganguly, Chamak, Rakib, Saeed Hossen, Biswas, Satyendra N.

2023 6th International Conference on Electrical Information and Communication Technology (EICT)