Jing, T., Yuan, F., Hou, S., & Bai, L. (2024). CPLD-Based Measurement of FPGA Boot Time. 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET), Semiconductor and Electronic Technology (ISSET), 2024 3rd International Symposium on, 566-571. https://doi.org/10.1109/ISSET62871.2024.10779629
Chicago-referens (17:e uppl.)Jing, Tao, Feng Yuan, Siyuan Hou, och Lingqin Bai. "CPLD-Based Measurement of FPGA Boot Time." 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET), Semiconductor and Electronic Technology (ISSET), 2024 3rd International Symposium on 2024: 566-571. https://doi.org/10.1109/ISSET62871.2024.10779629.
MLA-referens (9:e uppl.)Jing, Tao, et al. "CPLD-Based Measurement of FPGA Boot Time." 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET), Semiconductor and Electronic Technology (ISSET), 2024 3rd International Symposium on, 2024, pp. 566-571, https://doi.org/10.1109/ISSET62871.2024.10779629.
