A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration - Yu, Yan; Luo, Deng; Chen, Jianjun; Guo, Yang; Liang, Bin; Chi, Yaqing; Sun, Hanhan; Xiao, Jing; Gao, Hao; Tao, Ming; Tang, Kai (2025 IEEE International Solid-State Circuits Conference (ISSCC), Solid-State Circuits Conference (ISSCC), 2025 IEEE International, 2025)