APA (7th ed.) Citation

Sun, D., Bu, F., Ye, Q., Li, S., Gao, Y., Wang, B., . . . Zhu, Z. (2025). 19.11 A 13GHz Charge-Pump PLL Achieving $\mathbf{15.8}\mathbf{fs}_{\mathbf{rms}}$ Integrated Jitter and -98.5dBc Reference Spur. 2025 IEEE International Solid-State Circuits Conference (ISSCC), Solid-State Circuits Conference (ISSCC), 2025 IEEE International, 68, 344-346. https://doi.org/10.1109/ISSCC49661.2025.10904662

Chicago Style (17th ed.) Citation

Sun, Depeng, et al. "19.11 A 13GHz Charge-Pump PLL Achieving $\mathbf{15.8}\mathbf{fs}_{\mathbf{rms}}$ Integrated Jitter and -98.5dBc Reference Spur." 2025 IEEE International Solid-State Circuits Conference (ISSCC), Solid-State Circuits Conference (ISSCC), 2025 IEEE International 68 (2025): 344-346. https://doi.org/10.1109/ISSCC49661.2025.10904662.

MLA (9th ed.) Citation

Sun, Depeng, et al. "19.11 A 13GHz Charge-Pump PLL Achieving $\mathbf{15.8}\mathbf{fs}_{\mathbf{rms}}$ Integrated Jitter and -98.5dBc Reference Spur." 2025 IEEE International Solid-State Circuits Conference (ISSCC), Solid-State Circuits Conference (ISSCC), 2025 IEEE International, vol. 68, 2025, pp. 344-346, https://doi.org/10.1109/ISSCC49661.2025.10904662.