Wang, K., Wan, M., & Fang, W. (2025). An Improved 3D Systolic Architecture Design Using A Combination of Sub-Array Partitioning and Hierarchical Stacking Methods. 2025 IEEE International Conference on Consumer Electronics (ICCE), Consumer Electronics (ICCE), 2025 IEEE International Conference on, 1-5. https://doi.org/10.1109/ICCE63647.2025.10929973
Chicago-referens (17:e uppl.)Wang, Kai-Li, Meng-Ting Wan, och Wai-Chi Fang. "An Improved 3D Systolic Architecture Design Using A Combination of Sub-Array Partitioning and Hierarchical Stacking Methods." 2025 IEEE International Conference on Consumer Electronics (ICCE), Consumer Electronics (ICCE), 2025 IEEE International Conference on 2025: 1-5. https://doi.org/10.1109/ICCE63647.2025.10929973.
MLA-referens (9:e uppl.)Wang, Kai-Li, et al. "An Improved 3D Systolic Architecture Design Using A Combination of Sub-Array Partitioning and Hierarchical Stacking Methods." 2025 IEEE International Conference on Consumer Electronics (ICCE), Consumer Electronics (ICCE), 2025 IEEE International Conference on, 2025, pp. 1-5, https://doi.org/10.1109/ICCE63647.2025.10929973.
