APA (7th ed.) Citation

Hua, S., Wang, D., Wang, L., Liu, Y., & Li, J. (2015). A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. 2015 IEEE 11th International Conference on ASIC (ASICON), ASIC (ASICON), 2015 IEEE 11th International Conference on, 1-4. https://doi.org/10.1109/ASICON.2015.7517127

Chicago Style (17th ed.) Citation

Hua, Siliang, Donghui Wang, Leiou Wang, Yan Liu, and Jiarui Li. "A PVT-insensitive All Digital CMOS Time-to-digital Converter Based on Looped Delay-line with Extension Scheme." 2015 IEEE 11th International Conference on ASIC (ASICON), ASIC (ASICON), 2015 IEEE 11th International Conference on 2015: 1-4. https://doi.org/10.1109/ASICON.2015.7517127.

MLA (9th ed.) Citation

Hua, Siliang, et al. "A PVT-insensitive All Digital CMOS Time-to-digital Converter Based on Looped Delay-line with Extension Scheme." 2015 IEEE 11th International Conference on ASIC (ASICON), ASIC (ASICON), 2015 IEEE 11th International Conference on, 2015, pp. 1-4, https://doi.org/10.1109/ASICON.2015.7517127.